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OS-6546 Use PCID if KPTI is enabled

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          --- old/usr/src/uts/intel/sys/x86_archext.h
          +++ new/usr/src/uts/intel/sys/x86_archext.h
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  21   21  /*
  22   22   * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
  23   23   * Copyright (c) 2011 by Delphix. All rights reserved.
  24   24   * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
  25   25   */
  26   26  /*
  27   27   * Copyright (c) 2010, Intel Corporation.
  28   28   * All rights reserved.
  29   29   */
  30   30  /*
  31      - * Copyright 2017 Joyent, Inc.
       31 + * Copyright 2018 Joyent, Inc.
  32   32   * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
  33   33   * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
  34   34   * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
  35   35   */
  36   36  
  37   37  #ifndef _SYS_X86_ARCHEXT_H
  38   38  #define _SYS_X86_ARCHEXT_H
  39   39  
  40   40  #if !defined(_ASM)
  41   41  #include <sys/regset.h>
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 203  203   * Like some other leaves, but unlike the current ones we care about, it
 204  204   * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
 205  205   * with the potential use of additional sub-leaves in the future, we now
 206  206   * specifically label the EBX features with their leaf and sub-leaf.
 207  207   */
 208  208  #define CPUID_INTC_EBX_7_0_BMI1         0x00000008      /* BMI1 instrs */
 209  209  #define CPUID_INTC_EBX_7_0_HLE          0x00000010      /* HLE */
 210  210  #define CPUID_INTC_EBX_7_0_AVX2         0x00000020      /* AVX2 supported */
 211  211  #define CPUID_INTC_EBX_7_0_SMEP         0x00000080      /* SMEP in CR4 */
 212  212  #define CPUID_INTC_EBX_7_0_BMI2         0x00000100      /* BMI2 instrs */
      213 +#define CPUID_INTC_EBX_7_0_INVPCID      0x00000400      /* invpcid instr */
 213  214  #define CPUID_INTC_EBX_7_0_MPX          0x00004000      /* Mem. Prot. Ext. */
 214  215  #define CPUID_INTC_EBX_7_0_AVX512F      0x00010000      /* AVX512 foundation */
 215  216  #define CPUID_INTC_EBX_7_0_AVX512DQ     0x00020000      /* AVX512DQ */
 216  217  #define CPUID_INTC_EBX_7_0_RDSEED       0x00040000      /* RDSEED instr */
 217  218  #define CPUID_INTC_EBX_7_0_ADX          0x00080000      /* ADX instrs */
 218  219  #define CPUID_INTC_EBX_7_0_SMAP         0x00100000      /* SMAP in CR 4 */
 219  220  #define CPUID_INTC_EBX_7_0_AVX512IFMA   0x00200000      /* AVX512IFMA */
 220  221  #define CPUID_INTC_EBX_7_0_CLWB         0x01000000      /* CLWB */
 221  222  #define CPUID_INTC_EBX_7_0_AVX512PF     0x04000000      /* AVX512PF */
 222  223  #define CPUID_INTC_EBX_7_0_AVX512ER     0x08000000      /* AVX512ER */
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 445  446  #define X86FSET_AVX512VPOPCDQ   59
 446  447  #define X86FSET_AVX512NNIW      60
 447  448  #define X86FSET_AVX512FMAPS     61
 448  449  #define X86FSET_XSAVEOPT        62
 449  450  #define X86FSET_XSAVEC          63
 450  451  #define X86FSET_XSAVES          64
 451  452  #define X86FSET_SHA             65
 452  453  #define X86FSET_UMIP            66
 453  454  #define X86FSET_PKU             67
 454  455  #define X86FSET_OSPKE           68
      456 +#define X86FSET_PCID            69
      457 +#define X86FSET_INVPCID         70
 455  458  
 456  459  /*
 457  460   * Intel Deep C-State invariant TSC in leaf 0x80000007.
 458  461   */
 459  462  #define CPUID_TSC_CSTATE_INVARIANCE     (0x100)
 460  463  
 461  464  /*
 462  465   * Intel Deep C-state always-running local APIC timer
 463  466   */
 464  467  #define CPUID_CSTATE_ARAT       (0x4)
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 703  706          /* bit 8 unused */
 704  707  #define XFEATURE_PKRU           0x200
 705  708  #define XFEATURE_FP_ALL \
 706  709          (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
 707  710          XFEATURE_AVX512 | XFEATURE_PKRU)
 708  711  
 709  712  #if !defined(_ASM)
 710  713  
 711  714  #if defined(_KERNEL) || defined(_KMEMUSER)
 712  715  
 713      -#define NUM_X86_FEATURES        69
      716 +#define NUM_X86_FEATURES        71
 714  717  extern uchar_t x86_featureset[];
 715  718  
 716  719  extern void free_x86_featureset(void *featureset);
 717  720  extern boolean_t is_x86_feature(void *featureset, uint_t feature);
 718  721  extern void add_x86_feature(void *featureset, uint_t feature);
 719  722  extern void remove_x86_feature(void *featureset, uint_t feature);
 720  723  extern boolean_t compare_x86_featureset(void *setA, void *setB);
 721  724  extern void print_x86_featureset(void *featureset);
 722  725  
 723  726  
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 737  740   * This structure is used to pass arguments and get return values back
 738  741   * from the CPUID instruction in __cpuid_insn() routine.
 739  742   */
 740  743  struct cpuid_regs {
 741  744          uint32_t        cp_eax;
 742  745          uint32_t        cp_ebx;
 743  746          uint32_t        cp_ecx;
 744  747          uint32_t        cp_edx;
 745  748  };
 746  749  
      750 +extern uint_t x86_use_pcid;
      751 +extern uint_t x86_use_invpcid;
      752 +
 747  753  /*
 748  754   * Utility functions to get/set extended control registers (XCR)
 749  755   * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
 750  756   */
 751  757  extern uint64_t get_xcr(uint_t);
 752  758  extern void set_xcr(uint_t, uint64_t);
 753  759  
 754  760  extern uint64_t rdmsr(uint_t);
 755  761  extern void wrmsr(uint_t, const uint64_t);
 756  762  extern uint64_t xrdmsr(uint_t);
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 881  887  #if defined(OPTERON_WORKAROUND_6323525)
 882  888  extern int opteron_workaround_6323525;
 883  889  extern void patch_workaround_6323525(void);
 884  890  #endif
 885  891  
 886  892  #if !defined(__xpv)
 887  893  extern void determine_platform(void);
 888  894  #endif
 889  895  extern int get_hwenv(void);
 890  896  extern int is_controldom(void);
      897 +
      898 +extern void enable_pcid(void);
 891  899  
 892  900  extern void xsave_setup_msr(struct cpu *);
 893  901  
 894  902  /*
 895  903   * Hypervisor signatures
 896  904   */
 897  905  #define HVSIG_XEN_HVM   "XenVMMXenVMM"
 898  906  #define HVSIG_VMWARE    "VMwareVMware"
 899  907  #define HVSIG_KVM       "KVMKVMKVM"
 900  908  #define HVSIG_MICROSOFT "Microsoft Hv"
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